Who should read it
Core reading for AI-infrastructure, inference-serving and systems-for-ML research roles, and an excellent systems paper for anyone who knows virtual memory: it explains why KV-cache memory management limits batch size and therefore throughput. Modelling-focused research roles and applied-AI roles only need the idea (paged KV blocks enabling larger batches and prefix sharing). It is not needed if you will not work on serving systems.
Study objectives
- Explain how KV-cache size grows with sequence length and batch size, and why reserving contiguous memory per request wastes it.
- Describe the block table, logical-to-physical block mapping, copy-on-write sharing and the attention-kernel changes the design requires.
- Explain the scheduling and preemption policy (swapping versus recomputation) and when each is cheaper.
- Critique the evaluation: workloads, request-arrival model, baselines (including reimplemented ones) and the normalized-latency metric.
Prerequisites
Main concepts to understand
- KV cache as the dominant dynamic memory consumer in LLM serving
- Reserved slots, internal fragmentation and external fragmentation when output lengths are unknown
- Fixed-size KV blocks, block tables and on-demand allocation (the paging analogy)
- Sharing blocks across sequences with reference counts and copy-on-write (parallel sampling, beam search, shared prefixes)
- Iteration-level batching combined with memory-aware admission
- Preemption with all-or-nothing eviction by swapping to CPU memory or by recomputation
- Kernel support for attention over non-contiguous blocks and fused block operations
What to inspect in the evaluation
- Workloads: requests synthesized from ShareGPT and Alpaca input and output lengths with Poisson arrivals at several rates; consider how burstiness or real timestamps could change the results.
- Metric: normalized latency (mean end-to-end latency divided by output length) against request rate; check whether tail latency or time to first token are reported and what the mean can hide.
- Baselines: FasterTransformer with a custom batching scheduler, and Orca reimplemented by the authors in three reservation variants (Oracle, Pow2, Max) because Orca was not publicly available; judge how faithfully a reimplementation represents the original.
- Models and hardware: OPT 13B, 66B and 175B and LLaMA 13B on A100 GPUs, with shorter traces for the largest model because of cost.
- Ablations (Section 7): kernel overhead microbenchmark, block-size sensitivity, and swapping versus recomputation; check which conclusions depend on the test machine’s CPU-GPU bandwidth.
- Memory-waste measurements in the introduction: check how the used fraction of KV memory is measured for each system.
Guarantees versus empirical results
Correctness or design arguments
- Design argument: with fixed-size blocks allocated on demand, waste is confined to the last partially filled block of each sequence and external fragmentation is eliminated.
- Copy-on-write sharing preserves the semantics of independent sequences while sharing physical blocks (design argument, no formal proof).
- All-or-nothing eviction keeps a sequence’s cache consistent because attention needs all of its earlier tokens (design rationale).
Empirical results (depend on setup)
- Higher throughput at comparable normalized latency than FasterTransformer and the Orca variants on the synthesized workloads.
- Larger effective batch sizes and memory savings for parallel sampling, beam search and shared prefixes.
- The overhead of the paged attention kernel relative to a contiguous kernel (kernel microbenchmark).
- The effect of block size and the relative cost of swapping and recomputation on the authors’ hardware.
Reading plan
- Pass 1 (20 minutes): abstract, the memory-waste figure in the introduction, Section 3 on memory challenges and the conclusion.
- Pass 2 (90 minutes): Section 4 (PagedAttention, KV cache manager, decoding scenarios, scheduling and preemption) next to an OS virtual-memory refresher, then the Section 6 setup and main figures.
- Pass 3 (3–5 hours, serving roles): write a toy block allocator with reference counts and copy-on-write, simulate admission under a Poisson trace with several block sizes, and compare it with contiguous reservation.
Discussion prompts
- Which virtual-memory ideas transfer directly to KV caches, and which do not (for example, there is no hardware TLB)?
- How might results change with real arrival timestamps, longer contexts or a prefix-heavy chat workload?
- Why use normalized latency, and which serving metrics (time to first token, inter-token latency, tail latency) would you add?
- When is recomputation cheaper than swapping, and how does the answer depend on hardware?
- What risks come from comparing against a reimplemented baseline, and how would you mitigate them?